1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming replacement gates structures on semiconductor devices and various semiconductor devices with replacement gates made using such methods.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
For many early device technology generations, the gate structures of most transistor devices, whether a planar device or a 3D device, have been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. The replacement gate technique has been employed on both planar and 3D devices, like FinFETs. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed.
FIGS. 1A-1K depict one illustrative prior art method for forming an HK/MG replacement gate structure using a replacement gate technique. As shown in FIG. 1A, an integrated circuit device 10 is comprised of a plurality of illustrative sacrificial gate structures 13. Each of the sacrificial agate structures 13 is comprised of a sacrificial gate insulation layer 14, e.g., a layer of silicon dioxide, and a sacrificial gate electrode 15, e.g., a layer of polysilicon. A gate cap layer 17, e.g., a layer of silicon nitride, is positioned above the sacrificial gate electrode 15. At the point of fabrication depicted in FIG. 1A, a layer of insulating material 18, e.g., a layer of flowable silicon dioxide, has been formed on the device 10. The sacrificial gate structures 13 and the gate cap layers 17 may be formed by forming the various layers of material across the substrate 12 and thereafter patterning the layers of material. The sidewall spacers 16 may then be formed by conformably depositing a layer of spacer material and thereafter performing an anisotropic etching process. The layer of insulating material 18 may be formed by performing a chemical vapor deposition process.
FIG. 1B depicts the device 10 after a chemical mechanical polishing (CMP) process has been performed to remove excess portions of the layer of insulating material 18 and to expose the gate cap layer 17. As shown in FIG. 1C, an etching process has been performed to remove a portion of, or recess, the layer of insulating material 18. The etching process is performed such that, after etching, the recessed surface 18R of the layer of insulating material 18 is positioned below the upper surface 15S of the sacrificial gate electrode 15. The material selected for the layer of insulating material 18 is typically selected based upon its ability to reliably fill the very small spaces between spacers 16 on adjacent replacement gate structures 13 as shown in FIG. 1A, e.g., a flowable oxide material may be the material selected for the layer of insulating material 18. While such a material may have good “fill” capabilities, it exhibits relatively poor etch selectivity when subjected to an etching process that will be performed later to remove silicon nitride materials. Thus, an upper portion of the layer of insulating material 18 is removed and replaced with a layer of insulating material that exhibits a better etch selectivity when exposed to an etching process that is performed to remove silicon nitride.
FIG. 1D depicts the device 10 after a layer of insulating material 20, e.g., an HDP oxide, has been deposited on the device and after a CMP process has been performed to remove excess amounts of the layer of insulating material 20. The CMP process exposes the cap layers 17 and spacers 16 for further processing. As shown in FIG. 1E, an etching process has been performed to remove the gate cap layers 17 and portions of the sidewall spacers 16. This etching process exposes the sacrificial gate electrodes 15 for further processing. FIG. 1F depicts the device 10 after one or more etching processes have been performed to remove the sacrificial gate electrode 15 and the sacrificial gate insulation layer 14 to thereby define a gate cavity 22 where a replacement gate structure will subsequently be formed. Typically, the sacrificial gate insulation layer 14 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 14 may not be removed in all applications. FIG. 1G depicts the device 10 after schematically depicted replacement gate structures 24 have been formed in the gate cavities 22. The materials used for such replacement gate structures 24 may vary depending upon the particular application. Even in cases where the sacrificial gate insulation layer 14 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the substrate 12 within the gate cavity 22. In one illustrative example, the replacement gate structure 24 is comprised of a high-k gate insulation layer, such as hafnium oxide, and one or more layers of metal. The layers of material that comprise the replacement gate structure 24 are sequentially deposited in the gate cavities 22 and one or more CMP processes are performed to remove excess portions of these layers of material to thereby arrive at the replacement gate structures 24 depicted in FIG. 1G, wherein the upper portions of the replacement gate structure 24 are separated from one another by the insulating material 20.
The aforementioned process flow is not without problems. As part of the process of forming the replacement gate structures 24, the device will typically be subjected to a pre-clean process, usually with HF acid, to insure that all non-desired materials are removed from the surface of the substrate 12 prior to forming the layers of material that will be part of the replacement gate structure 24. While the layer of insulating material 20 does exhibit better etch selectivity than the layer of insulating material 18 when exposed prior to an etching process designed to remove silicon nitride, the layer of insulating material 20 may be severely degraded or substantially consumed when exposed to this pre-clean process that uses HF acid. This becomes problematic as the gate pitch 13P (see FIG. 1D) on devices continues to shrink. For example, width 20X (see FIG. 1D) of the upstanding portions of the layer of insulating material 20 increases as the gate pitch 13P increases. Conversely, the width 20X decreases as the gate pitch 13P decreases. The thinner the width 20X, the more likely the upstanding portions of the layer of insulating material 20 may be completely consumed during the HF acid pre-clean process.
Although not drawn to scale, FIG. 1H depicts the situation where the gate pitch 13P1 is so small that all of the upstanding portions of the layer of insulating material 20 are consumed during the HF acid pre-clean process—compare FIGS. 1E and 1H. FIG. 1I depicts the device 10 after the replacement gate structures 24 have been formed on the device shown in FIG. 1H. Note dashed lines 20S indicate the absence of the upstanding portions of the layer of insulating material 20. As a result, excessive metal gate CMP is needed, otherwise there is no electrical isolation between the replacement gate structures 24 and the device will not operate as intended. In general, some of the problems associated with the loss or reduction in size of the upstanding portions of the layer of insulating material 20 is (1) loss of gate height and (2) it causes variations in the gate height of narrow-pitch devices and relaxed-pitch devices. In modern semiconductor device manufacturing, it is very common to use transistors that are formed with different pitches on the same substrate. The aforementioned difference in height in the final gate structures can create problems in later manufacturing operations that are performed to complete the device 10, e.g., CMP processes, etc.
Complete loss of the upstanding portions of the layer of insulating material 20 is not the only problem associated with the above-described prior art process flow. Although not drawn to scale, FIG. 1J depicts the situation where there is not a complete loss of the upstanding portions of the layer of insulating material 20. More specifically, in FIG. 1J, the gate pitch 13P2 is not so small that all of the upstanding portions of the layer of insulating material 20 are consumed during the HF acid pre-clean process. Nevertheless, the overall height 20A of the upstanding portions of the layer of insulating material 20 after the HF acid pre-clean process is complete is less than the height 20Y of the upstanding portions of the layer of insulating material 20 prior to the HF acid pre-clean process being performed—compare FIGS. 1D and 1J. FIG. 1K depicts the device 10 after the replacement gate structures 24 have been formed on the device shown in FIG. 1J. Note dashed lines 20S indicate the absence of the upstanding portions of the layer of insulating material 20. In the incomplete loss situation, the reduction in the size, i.e., width of the upstanding portions of the layer of insulating material 20, ultimately results in a narrower opening for a subsequent contact to land on the underlying source/drain region, thereby making processing more difficult and more likely to result in processing errors due to misalignment, incomplete or poor contact formation, etc. Additionally, even in the incomplete loss situation, due to the reduction in height of the upstanding portions of the layer of insulating material 20 after the silicon nitride etching process, the replacement gate structures 24 in FIG. 1K have a height 24S that is shorter than other gate structures on the device that have larger gate pitch dimensions. FIG. 1G depicts a final gate structure 24 that has a height 24T that is greater than the height 24S.
The present disclosure is directed to various methods of forming replacement gate structures on semiconductor devices and various semiconductor devices with replacement gates made using such methods that may solve or reduce one or more of the problems identified above.